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IRMCS2033
Address Byte
HP_A = 1
Data Byte 0
HP_A = 0
…………….
HP_A = 0
Data Byte N
HP_A = 0
Host Parallel Data Transfer Format
Figure 9 and Table 2 show read cycle timing for the host parallel interface. Figure 10 and Table 3 show write cycle
timing.
HP_nCS
HP_nWE
t HPWENS
t HPCSN
HP_A
t HPAS
t HPA
t AHPD
HP_D [7:0]
HP_nOE
t HPOENS
t HPZD
t HPOEN
VALID
t HPDZ
Figure 9. Host Parallel Read Cycle Timing
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
NOTE
S
t HPCSN
HP_nCS Period
70
ns
t HPWENS
t HPAS
HP_nWE Setup
HP_A Setup
40
40
ns
ns
Note 3
t AHPD
t HPZD
t HPDZ
HP_D [7:0] Access
HP_D [7:0] Active
HP_D [7:0] High Impedance
60
0
0
105
9
6
ns
ns
ns
t HPOENS
t HPOEN
HP_nOE Setup
HP_nOE Period
40
70
ns
ns
Note 3
Table 2: Host Parallel Read Cycle Timing
Note:
1.
HP_nOE, HP_nWE must be stable before the high to low transition of HP_nCS.
This document is the property of International Rectifier and may not be copied or distributed without expressed consent.
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